This book claims to be about principles and practices. Most of the prin Today, however cfm Fashion Design Essentials: Principles of Fashion Design. PDF Producer: Laung-Terng Wang, Cheng-Wen Wu, “VLSI test principles and architectures: design for testing from the design phase, that's what we call DFT. VLSI Test Principles and Architectures: Design for Testability. Edited by Laung- Terng Wang, Cheng-Wen Wu, and Xiaoqing Wen. Contact.
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Request PDF on ResearchGate | VLSI Test Principles and Architectures | This book is a comprehensive guide to new DFT methods that will show the readers. The book's focus on VLSI test principles and DFT architectures, while deemphasizing test algorithms, is an ideal choice for undergraduate. 2, Logic Simulation, pdf. 3, Fault Models, pdf. 4, Fault Collapsing, pdf L.T. Wang , C.W. Wu, and X. Wen, “VLSI Test Principles and Architectures”, Morgan.
Representative, commercially available compression tools are introduced so readers practitioners can appreciate what is best suited to their needs. Chapter 7 delves into the topic of logic diagnosis.
Techniques for combinational logic diagnosis based on cause—effect analysis, effect—cause analysis, and chip-level strategy are first described. Then, innovative techniques for scan chain diagnosis and logic BIST diagnosis are explained in detail.
Chapter 8 and Chapter 9 cover the full spectrum of memory test and diagnosis methods.
In both chapters, after a description of basic memory test and diagnosis concepts, memory BIST and memory BISR architectures are then explained in detail. Memory fault simulation, a unique topic, is also discussed in Chapter 8. Chapter 10 covers boundary scan and core-based testing for board-level and system-level testing. The newly endorsed IEEE core-based testing standard is then described.
Chapter 11 is devoted to analog and mixed-signal testing. Important analog circuit properties and their defect mechanisms and fault models are described first. Methods for analog circuit testing are then explained. The IEEE standard for digitizing waveform recorders is then explained. A related standard, IEEE Chapter 12 is devoted to test technology trends in the nanometer age.
It presents an international test technology roadmap to put these new trends in perspective and predicts test technology needs in the coming 10 to 15 years, such as better methods for delay testing, as well as coping with physical failures, soft errors, and reliability issues. It is also intended for use as a reference book for researchers and practitioners.
The book is self-contained, with most topics covered extensively from fundamental concepts to current techniques used in research and industry. We assume that the students have had basic courses in logic design, computer science, and probability theory. Attempts are made to present algorithms, where possible, in an easily understood format.
In order to encourage self-learning, readers are advised to check the Elsevier companion Web site www. Professors will have additional privileges to assess the solutions directory for all exercises given in each chapter by visiting www. Laung-Terng L. Without their strong commitments to contributing the chapters and sections of their specialties to the book in a timely manner, it would not have been possible to publish this fundamental DFT textbook, which covers the most recent advances in VLSI testing and DFT architectures.
We also would like to give additional thanks to the reviewers of the book, particularly Prof. Sudhakar M. Reddy University of Iowa , Prof.
Kewal K. Saluja University of Wisconsin—Madison , Prof. Yinhe Han and Dr. Kenneth P. Semiconductor Solutions Network Co. Special thanks also go to many colleagues at SynTest Technologies, Inc. Ravi Apte, Jack Sheu, Dr. Chapter 6 Agilent Technologies, Inc. Wang, Ph.
Encouraged by his advisor, Professor Edward J. Under his leadership, the company has grown to more than 50 employees and customers worldwide. The design for testability DFT technologies Dr.
Wang has developed have been successfully implemented in thousands of ASIC designs worldwide. He has filed more than 25 U. He spearheaded efforts to raise endowed funds in memory of his NTU chair professor, Dr. Irving T.
Since , he has helped establish a number of chair professorships, graduate fellowships, and undergraduate scholarships at Stanford University and National Taiwan University, as well as Xiamen University, Tsinghua University, and Shanghai Jiaotong University in China.
Cheng-Wen Wu, Ph. His research interests are in the areas of memory BIST and diagnosis, memory built-in self-repair BISR , and security processor design with related system-on-chip test issues. He has published more than journal and conference papers.
Among the many honors and xxx About the Editors awards Dr. Xiaoqing Wen, Ph. In , Dr. Wen joined the Kyushu Institute of Technology. He has published more than 50 journal and conference papers and has been a co-inventor with Dr. Laung-Terng Wang of more than 15 U. Small-scale integration SSI devices, with tens of transistors in the early s, and mediumscale integration MSI devices, with hundreds of transistors in the late s, were relatively simple to test.
However, in the s, large-scale integration LSI devices, with thousands and tens of thousands of transistors, created a number of challenges when testing these devices.
In the early s, very-large-scale integration VLSI devices with hundreds of thousands of transistors were introduced. Steady advances in VLSI technology have resulted in devices with hundreds of millions of transistors and many new testing challenges. Note that not all inputs need to have defects and transition fault coverage alone cannot accurately logic values in order to detect the primary fault.
If many assess the capability of a transition delay test pattern set in inputs remain unspecified indicated by Xs in Fig. In addition, output deviation more secondary faults can be further targeted for fault can be used as an effective surrogate metric .
This process is called dynamic compaction, which helps reduce final test pattern count. Even after dynamic III. Such Test generation for a large combinational circuit may an input combination is called a test cube. X-filling is then take days, if not weeks, to complete.
For a sequential circuit, used to assign logic values to Xs in a test cube so as to obtain even a modest one, its test generation time can easily become 2 prohibitively long. This means that industrial circuits, which combinational portion, external inputs are called primary are mostly sequential in nature with tens of thousands of flip- inputs PIs and internal inputs from the FFs are called flops FFs , cannot be tested as is. A typical solution is to pseudo primary inputs PPIs.
In addition, external outputs convert a sequential circuit into a scan design so that its are called primary outputs POs and internal outputs to the testing can be conducted through targeting the combinational FFs are called pseudo primary outputs PPOs. Since PPIs portion of the original circuit.
Scan design is the most are hard to control and PPOs are hard to observe, faults in fundamental type of design for testability DFT . The basic idea is to replace all functional which all test tasks test generation, test application, and test FFs with scan FFs and connect them into scan chains.
In a scan design, functional FFs are first replaced with scan FFs. Then, scan FFs are connected into scan chains. An example is shown in Fig. Here, the D inputs of all scan FFs come from the combinational portion, while the SI input of each scan FF except the first one is connected to the Q output of the preceding scan FF in a scan chain.
The SI input of the first scan FF in a scan chain is directly controllable from the outside, and it is called the scan input SI of the scan chain. On the other hand, the Q input of the last scan FF in a scan chain is directly observable from the outside, and it is called the scan output SO of the scan chain.
Note that a scan design may have multiple scan chains and its number is usually limited by the number of pins available for corresponding SIs and SOs of the scan chains. Basically, two operation modes i.
These two modes are switched back and forth by using the SE signal . The equivalent circuit for shift mode is shown in Fig. It can be seen that the scan chain operates as a shift register in shift mode, in which the PPI values test stimulus for a new test pattern are shifted-in serially from SI and the PPO values test response for the previous test pattern are shifted-out serially from SO.
It is clear that with this shift register function provided in shift mode, test stimuli can be easily set to all PPIs and test responses from all PPOs can be easily observed. Note that N shift clock pulses need to be applied, where N is the length of the longest scan chain in the scan design. The equivalent c Scan design circuit for capture mode is shown in Fig. Obviously, Figure 3. Example of Scan Design. Basically, one or two capture A. For the in order to be shifted-out in the next shift operation.
At-Speed Scan Testing for the scan design shown in Fig. Three shift clock Shrinking feature sizes and increasing clock frequencies pulses are applied in shift mode since the scan chain has have made timing-related defects a major cause for failing three scan FFs. In capture mode, one capture clock pulse is VLSI circuits. Testing for such defects needs delay test applied long after the last shift clock pulse is applied.
Such patterns, which are usually generated with the transition scan testing is called slow-speed scan testing, which is used delay fault model or the path delay fault model.
In addition to test for non-delay-type faults with test patterns generated to delay test patterns, delay test application is usually for stuck-at faults, bridging faults, etc. Note can propagate to the end point of the path in a functional that scan test patterns are generated for the combinational clock cycle is checked by making use of scan design .
Since test generation and test capture LOC , as described below. At-Speed Scan Testing. The LOS scheme is illustrated in Fig. This scheme generates transitions at the start points of sensitized paths by the differences of logic values loaded into FFs by the next- to-last shift clock pulse SL-1 and the last shift clock pulse SL. Test responses are captured by the capture clock pulse C1.
Note that the time between the last shift clock pulse SL and the capture clock pulse C1 is set to be equal to the functional cycle in order to realize at-speed scan testing. The LOC scheme is illustrated in Fig. Different from the LOS scheme, this scheme generates transitions at the start points of sensitized paths by the differences of logic values loaded into FFs by the last shift clock pulse SL and the first capture clock pulse C1.
Test responses are captured by the second capture clock pulse C2. Note that the time between the first capture clock pulse C1 and the second capture clock pulse C2 is set to be equal to the functional c Timing waveform cycle in order to realize at-speed scan testing. Since two Figure 4. Example of Scan Testing.
This is because it provides better controllability and observability due to the use of a single capture clock. Transition delay test patterns are widely used for at-speed scan testing. However, high transition fault coverage may not directly translate into high at-speed scan test quality. This is because at-speed scan test quality also depends on the relations among 1 the lengths of sensitized paths, 2 the extra delays caused by timing-related defects, and 3 the length of the test cycle, as illustrated in Fig.
Especially, Figure 7. Gap between Functinoal Power and Test Power. As shown in Fig. Only when the sensitized path is testing. Such test generation is called small-delay test to a significantly low level.
However, this effort does not generation . The quality of a small-delay test pattern set help reduce scan test power. Due to constraints from test can be assessed with the SDQL metric .
This inevitably increases switching activity, resulting in excessive test power. For example, it was reported in that test power could be 2X higher than functional power . This gap has been steadily growing and was found to have reached 5X in .
Excessive test power is starting to cause various problems in scan testing, especially in at-speed scan testing. Figure 6. However, functional power and test power have so different characteristics that, even if functional power is reduced to a low level, scan test power may still be excessively high to cause serious problems in testing . Power Disspipation There are two types of power: dynamic power and static power.
Dynamic power depends on operation-independent factors supply voltage, load capacitance, frequency and operation-dependent factors switching activity level , while static power depends on operation-independent factors Figure 8.
Their impacts are illustrated in Fig. Clearly, this leads to unacceptably high test-power-induced yield loss. In order to address the capture power problem, over- designing the power supply network is not a viable solution. Generally, this problem has to be solved by reducing switching activity caused by transition launch also referred to as launch switching activity LSA through low-capture- power test generation or DFT techniques [, 16].
It then discussed the impact of scan test power. Wang, Y. Chang, and K. Tim Cheng, Eds. Figure 9. Abramovici, M. Breuer, and A.